^ 'The Sandy Bridge Review: Intel Core i7-2600K, i5-2500K and Core i3-2100 Tested'.^ a b c 'Intel's Second-Gen Core CPUs: The Sandy Bridge Review - Sandy Bridge's Secret Weapon: Quick Sync'.Nvidia NVENC, Nvidia's equivalent SIP core.Video Coding Engine, AMD's equivalent SIP core.Intel Clear Video, video decoding using a general purpose Intel GPU.Operating system support Ĭertain low-end and high-end parts (including multi-socket Xeons, and some Extreme Edition CPUs expected to be used with a dedicated GPU) do not contain the hardware core to support Quick Sync. Version 7 (Ice Lake) The Ice Lake (microarchitecture) adds VP9 4:4:4 decoding, VP9 encoding (up to 10-bit and 4:4:4), HEVC 4:2:2 and 4:4:4 decoding and encoding, HDR10 Tone Mapping and Open Source Media Shaders.
#Intel quicksync driver full#
Version 6 (Kaby Lake, Coffee Lake, Whiskey Lake) The Kaby Lake and Coffee Lake microarchitecture adds full fixed-function H.265/HEVC Main10/10-bit encoding and decoding acceleration and full fixed-function VP9 8-bit and 10-bit decoding acceleration and 8-bit encoding acceleration. Version 5 (Skylake) The Skylake microarchitecture adds a full fixed-function H.265/HEVC main/8-bit encoding and decoding acceleration, hybrid and partial HEVC main10/10-bit decoding acceleration, JPEG encoding acceleration for resolutions up to 16,000×16,000 pixels, and partial VP9 encoding and decoding acceleration. Also, it has two independent bit stream decoder (BSD) rings to process video commands on GT3 GPUs this allows one BSD ring to process decoding and the other BSD ring to process encoding at the same time. Version 4 (Broadwell) The Broadwell microarchitecture adds VP8 hardware decoding support. This generation of Quick Sync supports the H.264/MPEG-4 AVC, VC-1 and H.262/MPEG-2 Part 2video standards. Version 3 (Haswell) The Haswell microarchitecture implementation is focused on quality, with speed about the same as before (for any given clip length vs. Version 2 (Ivy Bridge) The Ivy Bridge microarchitecture included a 'next-generation' implementation of Quick Sync. Version 1 (Sandy Bridge) Quick Sync was initially built into some Sandy Bridge CPUs, but not into Sandy Bridge Pentiums or Celerons. The older Clarkdale microarchitecture had hardware video decoding support, but no hardware encoding support it was known as Intel Clear Video. Quick Sync was first unveiled at Intel Developer Forum 2010 (September 13) but, according to Tom's Hardware, Quick Sync had been conceptualized five years before that.
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